This invention relates to accessing data in memory arrangements and, more particularly, to data processing systems and methods involving data access in virtual memory for which multiple banks of data are concurrently opened.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased fast data-storage capability. For many applications, this has translated to an increased number of memory cells in a given chip size (or real estate area). Even with such higher-density memory circuits, there are still needs to increase the data processing capacity of CPUs, and this in turn places the demands on the associated resources, such as the system""s read-write memory. This is particularly true with certain CPUs, such as Very Long Instruction Word (VLIW) and Reduced Instruction Set Computing (RISC) processors, that require more memory capacity than the more widely used Complex Instruction Set Computing (CISC) CPUs and also require higher memory bandwidth.
One common approach for increasing the data processing capacity of a CPU is to employ virtual memory and memory address mapping. In systems that employ virtual memory, when the CPU is accessing read-write memory (e.g., DRAM), it is important for DRAM subsystems to allow fast access to the whole virtual memory page, because the code/data in that page is likely to be related and accessed relatively often. It is not important that DRAM subsystems be configured for optimal access times for accesses outside of the virtual memory page, since the DRAM controller would possibly permit such accesses anywhere in physical memory without knowledge as to where such accesses would ultimately be made.
In many virtual memory systems, the size of an open DRAM page is not as big as a virtual memory page. This relationship is dependent upon the organization of the memory in the system. In such systems where the open DRAM page size is smaller, if the memory address (MA) map does not have the bank address (BA) mapping to the next highest address bits, a contiguous open DRAM page as big as a virtual page would not be viable. For example, if the DRAM page side is 2 K bytes, but the virtual page size is 4 K bytes (or larger), CPU-to-DRAM performance is not optimized without the ability to use an open DRAM page as big as a virtual page. Further, in systems where a bank of DRAM is capable of supporting a page size as big as the virtual memory page, CPU-to-DRAM performance is degraded if multiple DRAM pages are mapped such that portions of them map onto a single virtual memory page.
Accordingly, there is a need for a memory access approach that permits multiple banks of data to be concurrently opened and that improves CPU-to-DRAM performance for virtual memory access.
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing storage data in a computer system having address and control signals for selecting data, components and/or devices. The process involves providing a plurality of addressable banks of memory cells; accessing the memory cells by addressing arrays in the banks via column and row bits; and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, the next highest group of the address bits directed to select bank address bits, and the next highest group of the address bits directed to select the row address bits.
Another specific implementation of the present invention is directed to a computer system configured to access data in a memory arrangement. The system includes a computer system arrangement comprising: a CPU circuit; a memory arrangement arranged in a plurality of addressable banks of memory cells and having arrays in the banks addressable via column and row bits for accessing the memory cells; and a memory mapping circuit adapted to direct address and control signals generated by the CPU circuit to select the addressable column address and row address bits with a lower order group of the CPU address bits directed to select the column address bits, the next highest group of the CPU address bits directed to select bank address bits, and the next highest group of the CPU address bits directed to select the row address bits.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.